8-bit serial-in/parallel-out shift register general description 74hc164 is fabricated in the high-speed silicon gate cmos technology. it has the high noise immunity and low power consumption of standard cmos integrated circuits. it also offers speeds comparable to low power schottky devices (ls-ttl). this 8-bit shift register has and-gated serial inputs and clear. each register bit is a d-type master-slave flip-flop. inputs a & b permit complete control over the incoming data. a low at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. a high level on one input enables another input, which will then determine the state of the first flip-flop. data at the serial inputs may be changed while the clock is high or low, but only data meeting the setup and hold time requirements will be entered. data is serially shifted in and out of the 8-bit register during the positive edge of the clock pulse. clear is independent of the clock and accomplished by a low level at the clear (cl) input. 74hc164 logic is functionally as well as pin-out compatible with the standard ls164. all inputs are protected from esd damage by internal diode clamps to vcc and ground. features ? wide operating supply voltage range: 2-6v. ? asynchronous master reset cl active at low ? date serially shifted at the positive edge of clock ck ? low input current: < 1 a. ? low quiescent supply current: 80 a maximum ? output driving capability: standard logic diagram ck cl serial inputs a b q q 1 q 2 q 3 q 4 q 5 q 6 q 7 8 ck cl ck d q ck cl ck d q ck cl ck d q c k cl ck d q ck cl ck d q ck cl ck d q ck cl ck d q ck cl ck d q 3 4 5 6 10 11 12 13 1 2 8 9 functional description 1. truth table inputs outputs cl ck a b q 1 q 2 ? q 8 l x x x l l l h l x x q 1o q 2o q 8o h h h h q 1n q 7n h l x l q 1n q 7n h x l l q 1n q 7n h = high level (steady state). l= low level (steady state) x = don?t care (any input, including transitions) = transition from low to high level. q 1o , q 2o , q 8o = the level of q1 , q2 , q8 , respectively, before the indicated steady state input conditions were established. q 1n , q 7n = the level of q1 or q7 before the most recent transition of the clock; indicates a one-bit shift . q 1 q 2 q 3 q 4 q 8 q 7 q 6 q 5 a b gnd vcc cl ck WS74HC164 1 7 14 8
2 2. logic waveform absolute maximum ratings parameter value unit dc supply voltage (vcc) - 0.5 ~ + 7.0 v dc input or output voltage (v in , v out ) -0.5 to vcc +0.5 v dc current drain per pin, any output (i out ) 25 ma dc current vcc or gnd (icc) 50 ma storage temperature( t stg ) -65 ~ +150 power dissipation (p d ) 500 mw note 1: absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. recommended operating conditions parameter min. typ. max. unit dc supply voltage (vcc) 2 5 6 v input / output voltage (v in , v out ) 0 vcc v vcc = 2 v 1.5 vcc = 4.5 v 3.15 v ih high-level input voltage vcc = 6 v 4.2 v vcc = 2 v 0.5 vcc = 4.5 v 1.35 v il low-level input voltage vcc = 6 v 1.8 v vcc = 2 v 1000 vcc = 4.5 v 500 input rise/fall times (t r /t f
3 dc electrical characteristics ( apply across temperature range unless otherwise s pecified) t a 25 o c parameter test conditions vcc min. typ. max. min. max. unit 2v 1.9 1.998 1.9 4.5v 4.4 4.499 4.4 i oh = -20ua 6v 5.9 5.999 5.9 i oh = -4ma 4.5v 3.98 4.3 3. 84 v oh v i =v ih or v il i oh = -5.2ma 6v 5.48 5.8 5. 34 v 2v 0.002 0.1 0.1 4.5v 0.001 0.1 0.1 i oh = 20ua 6v 0.001 0.1 0.1 i oh = 4ma 4.5v 0.17 0.26 0.33 v ol v i =v ih or v il i oh = 5.2ma 6v 0.15 0.26 0.33 v i i v i = v cc or 0 6v d 0.1 d 100 d 1000 na i cc v i = v cc or 0, i o = 0 6v 8 80 a c i 2v 6v 3 10 10 pf timing requirements over recommended operating temperature range (unless otherwise noted) t a 25 o c parameter vcc min. max. max. unit 2v 6 5 4.5v 31 25 f clock clock frequency 6v 36 28 mhz 2v 100 125 4.5v 20 25 cl low 6v 17 21 2v 80 100 4.5v 16 20 t w pulse duration ck high or low 6v 14 18 ns 2v 100 125 4.5v 20 25 data 6v 17 21 2v 100 125 4.5v 20 25 t s setup time before ck 17 21 ns 2v 5 5 4.5v 5 5 t h hold time data after ck 5 5 ns in.
4 ac electrical characteristics (c l =50pf) t a 25 o c parameter from input to output vcc min. typ. max. min. max. unit 2v 6 10 5 4.5v 31 54 25 f max 6v 36 62 28 mhz 2v 140 205 255 4.5v 28 41 51 t phl cl any q 6v 24 35 46 ns 2v 115 175 220 4.5v 23 35 44 t pd ck any q 6v 20 30 38 ns 2v 38 75 95 4.5v 8 15 19 t t 6v 6 13 16 ns parameter test conductions typ. unit c pd power dissipation capacitance t a =25 o c, no load 135 pf note 3 : c pd determines the no load dynamic power consumption , p d =c pd* vcc 2 * f i + icc * vcc, and the no load dynamic current consumption, is = c pd * vcc * f i + icc. ac switching waveform and ac test circuit ac switching waveform 50% 50% ts (data) 1/f max 50% 10% 10% 50% 90% 90% tf tr tw (ck) clock data gnd vcc 50% vcc gnd vcc gnd 50% 50% tw (cl) clear th ts (cl) tplh q tphl 50% 50% voh vol 50% tphl
5 c l q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 8 cl a b ck inputs ac testing circuit pin description pin no. symbol description 1, 2 3, 4, 5, 6, 10, 11, 12, 13 7 8 9 14 a, b q 1 ? q 8 gnd ck cl v cc data inputs outputs ground (0v) clock input (active at rising edge) master reset input (active at low) positive power supply q 1 q 2 q 3 q 4 q 8 q 7 q 6 q 5 a b gnd vcc cl ck 1 7 14 8 q 1 q 2 q 3 q 4 3 q 5 q 6 q 7 q 8 4 5 6 10 11 12 13 1 2 a b 8 9 ck cl pin configuration (dip14) log ic symbol pad diagram the coordinate of each pad q 1 (-395.1, -452.8) q 5 (305.0, 362.8) q 2 (-138.3, -452.8) q 6 ( 48.2, 362.8) q 3 ( 149.9, -452.8) q 7 (-240.0, 362.8) q 4 (355.4, -308.2) q 8 (-445.5, 214.6) gnd (355.4, - 82.2) vcc (-445.5, - 3.8) ck (338.7, 61.8) a (-428.8, -148.8) cl (340.6, 201.8) b (-430.7, -288.8) note 4: substrate should be connected to vcc or left it open. ck gnd pad size = 90 um x 90 um die size = 46 mil x 49 mil cl q 3 q 2 q 1 b a vcc hc164 q 8 q 4 q 5 q 6 q 7
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